The present invention relates to electronic circuits, and more particularly, to techniques for reconfiguring programmable circuit blocks.
Phase-locked loops (PLLs) are an essential building block of many integrated circuits, providing periodic signals for data recovery, data transfer, and other clocking functions. PLLs often supply a clock signal to one or more counters or dividers that divide a signal from an oscillator to a lower frequency clock signal for distribution around an integrated circuit or system. PLLs can have a voltage controlled oscillator, a current controlled oscillator, or a digitally controlled oscillator.
A programmable logic integrated circuit (IC), such as a field programmable gate array (FPGA) or a programmable logic device (PLD), typically contains programmable logic circuit blocks that can configured to perform a variety of functions. Some programmable ICs also include PLLs that have configurable settings.
When used inside a programmable logic IC, a PLL can have many configurations. Each configuration defines a specific application use in the user mode of the programmable logic IC. The requirements for input and output frequency, bandwidth, phase relationship, jitter budget, and many other feature requirements trigger a unique configuration for a PLL.
After a FPGA chip has been programmed, and a different configuration is needed, a new configuration is loaded into the chip. Loading a new configuration forces the chip to go out of user mode. As a result, the functionality of the system gets disrupted.
Therefore, it would be desirable to provide phase-locked loops that can be reconfigured without exiting user mode.